Hey all,

I'm a second year going to a Canadian university and have an hour long HireVue interview for a design and verification internship for Toronto. I have a week to prepare, and to be honest, I have no clue what to expect!

This will be my first technical interview and first one-way online interview, so if anyone is familiar with ARM's HireVue questions or has any info on this specific role's interview questions, it would mean a lot if you could share!

Cherry on top is I don't even have a JD since the original one is gone and it was a general one for all ARM positions.

For now, I plan on reviewing digital logic, sta, C (and maybe C++, not sure if I should or will have the time), and testbenches and writing modules with sv. Is there anything I'm missing in terms of technical content?

I'd be grateful for any advice!

what changes should I do ...and how good is it for internship and for entry level job.

For a brief background, after graduating in May 2023, I had to care for a family member, but, I was able to fit some projects in that time frame. All of the projects on my resume are implemented on a zybo z7-10 with a youtube video showing functionality along with the code on their respective github pages. I've submitted somewhere around 90+ applications to entry level positions and have not been offered a single interview. It's unfortunate because a denial email doesn't give any sort of criticism, which is what someone in my position absolutely needs. I can speculate about why this resume is resulting in me not getting passed screening, but I want to hear it from people in the industry. Primarily, my main questions are:

1. Does my resume show a candidate who has the technical skills needed for an entry-level position?
2. How large of a disadvantage am I at from graduating in 2023 with no professional experience?
3. What projects, skills, frameworks, etc. should I prioritize in order to become a more competitive entry-level candidate?
4. If you were in my position, how would you proceed with the next 6 months in order to maximize chances of getting interviewed?

I will reiterate that I want this feedback to be completely honest and uncensored. Not knowing exactly what is wrong with the way I'm presenting myself to employers is messing with my mental, so, any feedback is greatly appreciated.

I can't get them from the official website due to regional restrictions my IP is blocked, is there any torrent or download mirrors or some other way i can get those files?

A while ago I shared Parat, a solver whose "no" answers come with proofs that independent tools can check. v1.3 is out, and this time the target is one question: does a gate-level multiplier really compute a × b?

**The test case**

I made a 256-bit Booth multiplier with yosys 0.69: 503,960 AND gates, 512 output bits.

**The problem is building it, not proving it**

yosys's default flow (`synth -booth`) runs ABC's optimisation script. One step in that script, `&fraig -x`, gets about 82× slower every time the width doubles: 7 s at 64 bits, and the whole 128-bit build takes about 18 minutes. At 256 bits that means roughly 24 hours, so I could not build the full default netlist.

With only that one step left out (the rest of the default ABC script kept), the 256-bit netlist builds in 2 minutes and is only a few gates larger. It is still hard to prove: the previous version of Parat could not do even the 64-bit one in 25 minutes.

**Results (one 2-core machine)**

| width | AND gates | Parat: CORRECT + certificate | independent check |

|---|---|---|---|

| 64 | 33,014 | 42 s | CERTIFIED, 19 s |

| 128 | 128,357 | 114 s | CERTIFIED, 23 s |

| 256 | 503,960 | 13 min (1.2 GB certificate) | CERTIFIED, 3 min, 0.8 GB RAM |

A copy with one gate changed is answered INCORRECT, with a counterexample input.

**You don't have to trust Parat**

"CERTIFIED" means three checks, done by tools I did not write:

- pacheck2 (JKU Linz) checks the algebraic proof that the rebuilt circuit computes a × b

- drat-trim (UT Austin) checks 16 SAT proofs that your netlist and the rebuilt circuit give the same output on every input

- a small script checks that the certificate belongs to your circuit, and rebuilds every SAT file from your own netlist

One command runs all of it:

verify/verify_multiplier.sh circuit.aag pacheck drat-trim --cert prefix

**Still open**

The full default netlist (with `&fraig`) at 256 bits, because yosys itself needs about a day to make it. The full default netlists at 32–128 bits are proved (README, section 10).

**Try it**

- Repo: https://github.com/himanshu161106-crypto/parat

- Release (Linux, Windows, and new macOS builds): https://github.com/himanshu161106-crypto/parat/releases/tag/v1.3

- Netlists, build script (`make_nofraig.sh`), 64- and 128-bit certificates: `benchmarks/yosys_booth/`

- 256-bit certificate: on the release page

The macOS builds are new and not yet tested on a real Mac, so reports are very welcome. Free for personal and academic use.

The code was written by AI (Claude) under my direction; the ideas, the math and the testing are mine.

and question of mine:

1. If anyone knows how to make yosys/ABC run `&fraig -x` on a 256-bit multiplier in hours instead of a day (settings, a faster machine setup, or another way to get the same netlist), please tell me. I would love to try Parat on the full default netlist.

We’re hiring Hardware / SSD Validation Engineers for opportunities in Longmont, Colorado. We’re open to candidates at both junior and senior levels who have hands-on experience with hardware testing, SSD validation, or system-level testing.

🔹 Position 1: Hardware / SSD Validation Engineer — Junior

• Experience: 1–3 years
• Pay Rate: $55–$60/hour
• Required Skills:
  • Hands-on hardware testing or validation experience
  • Exposure to SSDs, NVMe, storage systems, or firmware testing
  • Understanding of system testing, debugging, and troubleshooting
  • Basic scripting knowledge in Python, C/C++, or similar languages is a plus

🔹 Position 2: Senior Hardware / SSD Validation Engineer

• Experience: 6+ years
• Pay Rate: $80–$85/hour
• Required Skills:
  • Strong experience in hardware, SSD, storage, or system validation
  • Hands-on experience with SSD/NVMe testing, firmware debugging, and root-cause analysis
  • Experience with regression testing, qualification testing, and test automation
  • Python, C/C++, or scripting experience
  • Ability to own validation activities and collaborate with hardware and firmware engineering teams

📍 Location: Longmont, Colorado
💰 Compensation: $55–$60/hr for junior candidates | $80–$85/hr for senior candidates
🏢 Work Arrangement: Onsite
📄 Employment Type: Contract

Interested? Send me a direct message with your resume or a brief summary of your hardware testing, SSD validation, or firmware experience. Please mention which experience level you're targeting.

If you know someone who might be a good fit, feel free to share this opportunity with them!

Hello everyone,

I had to get an FPGA for one of my uni classes and now that I’ve completed it I kinda just have it lying around. I was wondering what projects would be a good introduction to the FPGA (the lab was honestly just copy paste code and then wrestle with vivado for an hour). I have a Pynq Z2 FPGA and a little bit of verilog programming experience (although I’m very much still inexperienced in programming verilog)

I’m interested - what’s everyone’s most hated features of AMD/Intel FPGA toolchains?

I was having a discussion with my colleagues, for us it’s the overcrowded UI. So many cluttered buttons and features, half of which we never use…

We were debating about what the most hated features would be in the wider FPGA community, so I came to Reddit! Tell me your thoughts!

My cpu is alive on tang nano 9k

For context I am a US citizen. I feel like I have done a lot of learning, but I haven't had much opportunity to implement anything because my curriculum is not project-heavy at all. Honestly hard to not feel pessimistic about my chances. Any resume advice or project ideas would be appreciated.

After upgrading from Xcelium 24.03 to a release at or after 24.09, I see a change in the SDF annotation statistics. The option -sdf_splitvlog_setuphold appears to be the default now and when I use it in newest versions, I see a warning that this option is deprecated. As far as I can tell, there is no documented option to get the old behavior back.

What I see

My design uses only combined $setuphold timing checks in the specify block, and the SDF has combined SETUPHOLD entries as well. With -scopewise_sdfstats_log, the statistics table now also lists $setup and $hold as separate rows below $setuphold. In 24.03 only the combined $setuphold row was shown.

Minimal reproducer

design.sv:

module dut (input clk, input d, output reg q);
  always @(posedge clk) q <= d;

  specify
    (clk *> q) = (1.0, 1.0);
    $setuphold(posedge clk, d, 0.1, 0.1);
  endspecify
endmodule

test.sdf:

(DELAYFILE
  (SDFVERSION "2.1")
  (DESIGN "dut")
  (DATE "2026-10-14")
  (VENDOR "Example")
  (PROGRAM "Custom")
  (VERSION "1.0")
  (DIVIDER /)
  (VOLTAGE 1.0)
  (PROCESS "typ")
  (TEMPERATURE 25.0)
  (CELL
    (CELLTYPE "dut")
    (INSTANCE)
    (DELAY
      (ABSOLUTE
        (IOPATH clk q (1.0:1.0:1.0) (1.0:1.0:1.0))
      )
    )
    (TIMINGCHECK
      (SETUPHOLD d (posedge clk)
        (0.1:0.1:0.1)
        (0.1:0.1:0.1)
      )
    )
  )
)

sdf.cmd:

SDF_FILE          = "test.sdf",
SCOPE             = tb.u_dut,
LOG_FILE          = "sdf_annotation.log",
MTM_CONTROL       = "TYPICAL";

testbench.sv:

module tb;
  reg clk = 0;
  reg d = 0;
  wire q;

  dut u_dut (.clk(clk), .d(d), .q(q));

  initial begin
    #10 clk = 1; #10 clk = 0;
    #10 d = 1;
    #10 clk = 1; #10 clk = 0;
    #50 $finish;
  end
endmodule

Compile options: -timescale 1ns/1ps -sysv -sdf_cmd_file sdf.cmd -scopewise_sdfstats_log /dev/stdout

Resulting output (relevant part)

Path Delays   1   0   1   100.00
$setuphold    1   0.00   1.00   100.00
      $setup  1   0   1   100.00
       $hold  1   0   1   100.00

The summary lines still say No. of Tchecks = 1, and annotation is 100%. So I assume this is only a change in the report format and not in simulation behavior. Please correct me if that is wrong.

Question

Is there a documented (or undocumented) option or setting in the current releases that restores the old reporting/behavior, with combined $setuphold line and no $setup/$hold breakdown (even when I use combined $setuphold both in the .sdf and in the RTL files)?

Hey guys, this is my first time posting here.

Learning programming was quite fun. Follow a tutorial, type the code, then run.

But CPU design in Verilog or a logic simulator has been a whole different thing to me, I just can't find the resources to build my own computer. The best I could do was the accumulator-based Malvino/Eater SAP-1 following Pikuma - Digital Electronics.

So as a complete beginner, how do I learn how to design a computer?

In my thoughts:

Motherboard = PCB + Mount Ports

CPU = ASIC

RAM stick = PCB + DRAM ASICs

Can anyone guide me to how to learn such technology? Learning resources? Roadmap? How do I learn to learn to design hardware, that's where the problem lies.

I'm planning to make it an RV32IMF RISC-V computer that is general purpose. The main goal is to attach the accelerators I want (AI, 3D graphics, crypto miners, etc.) through peripherals.

Thanks for your time everybody and have a lovely day!

My boss and I need to access the co-simulation data after its execution in Ubuntu but we are unable to find the file where the results are stored. Does anyone where I could find them?

Thanks

A co-worker ran into the new BASIC tier limits in Vivado 2026.1. As far as I can tell, you get one ILA with at most 5 probes of up to 1024 bits each, and no debug insertion flows, so the ILA has to be instantiated in RTL. No System ILA or IBERT either.

Related threads:

• https://www.reddit.com/r/FPGA/comments/1thstyc/vivado_20261_basic_limited_debugging_xsim/
• https://adaptivesupport.amd.com/s/question/0D5Pd00001Y5fI4KAJ/new-licensing-options-for-v20261?language=en_US

The options we can think of so far:

• Pack signals into five wide probes and split them again with virtual buses in the hardware manager
• Use VIO and JTAG-to-AXI for status and control
• Write our own BRAM capture core and read it out over BSCANE2 or JTAG-to-AXI
• Use HDL Verifier’s FPGA Data Capture, if you already have a licence for it
• Stay on an older Vivado with the old licence file

Has anyone found something better, or did you just take the cost and buy a paid tier? I’d also like to hear if anyone has used an open-source capture core like LiteScope on Xilinx parts and how it compared to the ILA.

I have simply completely lost interest in FPGA design because of AI. I'm not here to argue about AI. I dont care if you love it or hate it. I personally simply have no interest in being in a position where the code for my designs is auto generated. Converting ny designs into RTL was my favorite part about the field, and the only reason I care to tolerate the other associated BS. And I'm already watching it get tossed out the window.

I'm curious what others think someone like me could find satisfaction from professionally.

i have applied 11 days ago and i still not get any reply. My doubt is that is the ats score actually matters,because i am applying through my resume that was made by tpc there was some limitation like one page and cannot mention rank and the project details are also small

How can I learn HDLs?

I’m a third-year Electronics and Communications Engineering student. I’m interested in this field and really want to work in it but I feel like I’ve never been good at programming. In the labs I’ve taken so far and the projects I’ve designed, the code I’ve written has always been 90% AI and at best 10% my own work. When it comes to bigger or more complex modules I automatically get scared

The other day when I went to see my professor for a project in the Digital Design with FPGAs course, he asked me about some of my modules, and I just stood there staring at him.

I worked really hard on the digital design course from the previous semester and passed it with flyin colors, but when it came to writing code, I am a real FAIL. I know I can fix this—I’m open to your advice. I really want to work in R&D, FPGAs, AI, Communications

my brain goes weird places during Uber shifts. i track carbs pretty tight for my A1C and got wondering if I could build a simple RISCV softcore on a dev board to log meals and glucose trends without relying on cloud apps. I have a cheap Tang Nano and basic Verilog. the idea is just MMIO for a keypad and small OLED, store entries to SD. looking about people building MIPS and RISCV cores from scratch got me thinking. how steep is the learning curve for someone with no CS background? FWIW I have a business degree and picked up Verilog from random tutorials. YMMV but I learn better when the project solves a real problem I have. is this too ambitious for a first real project after blinking LEDs?

October 28, 2026 from 2-3pm ET

REGISTER: https://bltinc.com/xilinx-training/blt-webinar-series/how-to-find-and-diagnose-fpga-timing-failures-with-amd-vivado-static-timing-analysis/

Can't attend live? Register to get the video!

How to Find and Diagnose FPGA Timing Failures with AMD Vivado Static Timing Analysis

BLT, an AMD Premier Design Services Partner and Authorized Training Provider, presents this webinar.

When an FPGA design fails timing, knowing where to look is the first step toward fixing it. Learn how Static Timing Analysis (STA) evaluates timing across your design and how to use the AMD Vivado™ Timing Summary report to identify timing failures and understand what is causing them. Explore setup and hold analysis, WNS, TNS, WHS, THS, failing endpoints, clock relationships, and timing constraints. Learn how to find critical timing paths, distinguish intra-clock and inter-clock paths, identify unconstrained paths, and understand timing exceptions and ignored paths. See how to drill into detailed path reports and customize the Timing Summary report to focus on the paths that matter most so you can get your design working.

This webinar includes a live demonstration and Q&A.

To see our complete list of webinars, visit our website: bltinc.com

I’ve reached the assessment centre for the Electronics Industrial Placement at Mercedes-AMG PETRONAS F1 in Brackley. I’m a second-year EEE student interested in FPGA/RTL design, with personal projects in SystemVerilog.

Does anyone know if F1 electronics team do sky FPGA/RTL work, or is it mainly PCB design, embedded systems and testing?

Hi i just wrote simple code for turning the led on ? And hello world program on the board . It didnt turn on the when i tried everything? Would the problem be with the board?

I have an older Basys 3 board that I want to mess around with and the tool chain looks like it needs to install 28GB on my drive. IS there a less bulky installation I can do to support this board?