My lil bro is currently interested in electronics and embedded systems.He wants to be a RTL Designer in future.

What advice would you give to him??

What Roadmap would you suggest??

Hello everyone, I'm curious: at what point do you stop taking on personal projects, or do you just reduce the time you allocate to them?

For context, I'm a 3rd-year undergrad, and I've had 3 tapeouts, all digital (a controller, a VGA, and, say, an SoC). I'm currently preparing for the 4th, a mixed-signal one. Open source flow.

I've also seen a few other opportunities, like AI-HDL, Chipalooza, and the Jane Street Emulator competition. I'm wondering if it's worth pursuing them to strengthen my portfolio or if I should let them go and focus on what I already have.

At what point do you stop chasing more opportunities and give yourself room to breathe? Is it worth pushing through burnout for better opportunities later, or is it okay to slow down and pursue these things when they come around again?

My goals are to:

1. Get to freelance working proficiency in mixed signals.

2. Gain experience as an intern and researcher.

3. Get into a fully funded master's program.

I don't really have an interest in a PhD, well, not yet. My GPA is around 3.0/4.0, and my university ranks around 1300 QS, so I've been trying to build a stronger project portfolio to make up for what might be a less competitive academic profile.

But I'm getting burned out from doing things because of these constraints rather than for the fun of it. I have previous designs that need revisions, a current design to work on, and competitions to plan for, all while funding myself as an undergraduate without a job in mixed signals.

Most times, I take embedded and simulation gigs to make ends meet, though I'm not able to save, as expenses take it all lol.

In short, is it okay to stop constantly trying to improve my skillset and trust that my existing work can get me somewhere, rather than being anxious about my GPA and other factors?

I'm planning to apply to companies like TSMC (DNA, DTP), MediaTek, Apple, a few lesser-known startups, and research labs, while also trying to maintain a good source of income.

I’m an undergraduate student, and have internship offers for an analog test engineer and HBM PHY validation engineer. They’re at the same company, and I’ve been told in the recruiting process that the analog test position deals with multiple IPs and is more lab work orientated. They’re both mostly post-silicon. My long-term goal is to transition into analog design, but there aren’t many undergraduate internships where I’m from, and my university doesn’t teach much at the undergrad level. What do the career trajectories look like for these two roles?

Hey everyone!

I currently have less than 5 years of experience in Analog. I am stuck in a job that unfortunately makes me unhappy (due to the environment, I still like analog design). I feel like if I don't make a change soon, my health will start to decline.

After a lot of search and interviews, landing a job in the current job market is not possible: I am too junior to be senior and too senior to be a junior, which leaves me in an awkward place.

I got this advice before and after some thought I think going the PhD route could be a good alternative. I already got some valuable exposure and experience in industry that I am sure gave me a different perspective than going from MsC to PhD directly and it would mean that I could more comfortably be considered for Senior positions when I am done (so with a PhD + experience).

Now I don't mind relocating all over Europe. After some search (not too detailed) the best countries in terms of compensation vs cost of living seem to be Germany and Switzerland. Not taking too much of a leap in terms of compensation is of course important as I want to keep my independence and in these countries a PhD student is treated as an employee (researcher) instead of getting a grant which I think is positive. Doing an industry funded PhD I feel would be the cherry on top also giving some chance to continue to work there after I am done (and if there is a good environment, I am too traumatized by the current one).

Does anyone have any insight to give on this perhaps pointing me to certain companies, professors, etc. That I can look into?

Thanks!

I'm a senior year student andy grad project is UCIE logical phy verification using uvm.

now i dont have much experience with verification because my laptop was broken for 2 months and now im studying uvm and struggling with it ,also reading from the ucie standard is very confusing and i cant seem to understand most the stuff there,

if any one can give me advice on either of those things please do

I am currently pursuing my MSc. in Germany. I started my master directly after my bachelor so I don't really have an industry exposure but I have gained a decent hands on Analog/Mixed Signal IC design through coursework and labwork. I'm looking for a project that I can work on over the next 2–3 months to improve my practical skills and prepare myself for industry roles (for now internship or werkstudent).

I would really appreciate suggestions from people who have been working in Analog/Mixed-Signal IC design. What kind of projects would you recommendl? I'd especially like to know what skills and design experience companies expect from students applying for internships or werkstudent positions.

Thanks!

Im learning systemverilog and uvm .

I tried eda playground but it is not validating my account

Could anyone help me

Recently got laid off from the company so looking for an opportunity in embedded systems field i have an experience of 2 years in embedded validation. If any advice always welcome

Would appreciate hearing about other people's experiences. I'm particularly curious about what the technical portion was like and which topics are worth focusing on.

Student project. Disclosure up front: the code was written by AI (Claude). My part was the ideas and the math behind them (for example the +/-/neutral "signal" for each variable, which turned out close to survey propagation, and treating a flip as a Boolean derivative), choosing what to attack and in what order, running the tests and races, and deciding what to publish. Parts of it also use standard methods from the SAT literature. Every result below is checked by independent tools, so nothing depends on trusting the code.

Parat takes a multiplier as an AIGER file and either proves out == a × b for ALL inputs, or gives a counterexample (a, b, wrong output, right output).

- 27 of the 28 unsigned GenMul architectures at 64 bits (array/Wallace/Dadda/counter trees with Kogge-Stone, Brent-Kung, carry-skip, ... adders), mostly under 1 s, each with a certificate that an independent checker (pacheck2) verifies. AMulet2 gets 8 of 28 in 300 s on the same files.

- Signed (two's complement) multipliers too: 26 of 27, detected automatically.

- Finds counterexamples for hidden single-gate bugs that random simulation misses (6 of 8 test designs).

Repo with all benchmarks, scripts and raw results: https://github.com/himanshu161106-crypto/parat

Limits: AIGER input (Verilog via yosys works), one Wallace + carry-lookahead design not proved, large certificates.

I'd love to hear what multiplier / datapath circuits you verify in real work, and what format they're in.

Hi . I have received one offer from Microsoft for L62
Base :45
Rsu :90k for 4 years
Jb :10 lakhs over 2 years

Is that good or low ball

Holding offer :
Base :42
Rsu :60k for 4 years
Joining bonus :8

Yeah, I know the odds of me landing an analog job after graduating with just a BS are like 0.1%. Regardless I want to ask, what are the best things I can do to stay on the right track and still try for it? Worst case scenario I go deeper into something I already like, and I join the club later down the line and get the MS. Coursework-wise I think I get the idea, all the analog electronics I can get my hands on, semiconductor devices, analog VLSI. But what about hands-on stuff I can do to build intuition toward analog IC design? Open PDKs, get familiar with ngspice/xschem? Should I bother with TinyTapeout?

Amd has come to for on campus placement drive, 10 to 12 month intern. It is taking:

2 technical rounds

1 hiring manager round

1 HR round

If anyone has gone through the process before, please give guidance on this. What to prepare, what type of questions asked, and anything else.

I just want insights on how the interview at Broadcom looks like. I have prepared typical topics needed for Physical Design but just want to know what type of questions do they normally ask. And what is the difficulty level from manager screening rounds to panel rounds.
Any information will be really helpful.
Thanks!

Hi everyone,

I'm a SoC Design Verification Engineer from South Korea, currently exploring job opportunities at semiconductor companies in Canada, such as AMD, NVIDIA, Qualcomm, and Amazon.

Here's a brief overview of my background:

• Master's degree in Electrical Engineering
• 3+ years of professional experience at a fabless semiconductor company
• SoC and IP-level Design Verification using SystemVerilog and UVM
• Experience with LPDDR5X memory subsystems and UCIe chiplet interconnects
• Functional verification, coverage closure, and performance bottleneck analysis
• Experience with one SoC tape-out

I'm currently in South Korea and have applied for Canada's IEC Working Holiday program, but my application hasn't been approved yet.

My plan is to use the IEC open work permit to pursue engineering opportunities in Canada without requiring employer sponsorship initially.

However, I'm aware that the work permit is temporary (up to 2 years), and I'm not sure how major semiconductor companies view candidates in this situation.

I've already started applying to some positions from Korea, but haven't had much luck so far.

I'd love to hear your thoughts:

1. Does this sound like a realistic strategy, or am I being too optimistic?
2. Would my background be competitive for Design Verification roles at major semiconductor companies in Canada?
3. Would a 2-year open work permit be a concern for recruiters or hiring managers, even if no initial sponsorship is required?
4. Should I keep applying from Korea, or would it make more sense to wait until my IEC is approved or I'm physically in Canada?

I'm not expecting an easy path, but I'd like to know whether this is a reasonable approach before investing more time and effort.

Any honest feedback, especially from engineers or recruiters in the Canadian semiconductor industry, would be greatly appreciated.

Thanks!

Anyone heard back?

I have found these in linkidin and got the mail to join it with the 50% off. Is this is a genuine platform or anything else🤷.

​

Hey everyone!

I have to choose one of the following projects for a 5-week Digital VLSI Circuits course, and I wanted to get some opinions on which would be the most worthwhile to pursue.

The four options are:

1. Transient Supply Droop Detector

2. Digital Frequency Multiplier

3. Process Variation Sensor

4. Time-to-Digital Converter (TDC)

The project will be implemented in Cadence Virtuoso, with transistor-level circuit design, simulation, layout, DRC/LVS verification, and post-layout parasitic extraction.

I'm looking for something that would look good on my resume, have practical industry relevance, and still be interesting enough to stand out. Ideally, I don't want to pick something that's too niche, but I also don't want to do a project that feels overly common or generic.

Since the timeline is only five weeks, I also want to choose something that is challenging enough to learn from without becoming unmanageable.

For those with experience in the semiconductor industry, VLSI design, or similar projects:

- Which of these would be most valuable from a hiring manager's perspective?

- Which has the best balance of industry relevance, learning opportunities, and feasibility within five weeks?

- Which would allow me to demonstrate meaningful circuit-level design and optimization rather than just reproduce an existing design?

- Are any of these particularly relevant to current industry work in digital IC design, timing, or power management?

I'd appreciate any suggestions, especially from people who have worked with these kinds of circuits in Virtuoso or have experience with digital VLSI interviews.

Thanks!

Has anyone found a way to automate the process of cleaning shorts in LVS? Any suggestions or ideas would be appreciated!

I got an interview with a PMIC team with a focus on PMIC control architecture. How should I prep for this? Any specific aspects I should focus on?

Hi yall, I have an interview at Samsung for Semiconductor Engineering Internship.

Anyone have experience with interviews at Samsung for similar roles and know how the interview questions might look like? Thanks

A few months back I asked you guys for your worst 24 hour ASIC design ideas and you guys suggested counting until the heat death of the universe.

Thus, I build out an ethernet connected beacon that broadcasts an ethernet frame over 100Mbps ethernet with the current uptime, and the ability to do so without overflow for the next 10^100 years.

Shortly after taping out the beacon with Tiny Tapeout, I got the opportunity to do a sponsored tapeout with wafer.space (very grateful to them) and with only 4 days to pull it off I decided that adding the beacon onto the chip was an awesome idea ...

So the beacon is getting its own chip 🥳 !

Fast forward October and the first 6 wafers have gotten back from the fab and the guys at wafer.space shared some really cool die shots.

As promised I will keep you guys updated with bring-up.

Original worst ASIC ideas thread: https://www.reddit.com/r/chipdesign/comments/1uk54wj/my_brain_is_fried_give_me_your_worst_48_hours/

Tapeout number 1 of the beacon (the full chip is tapeout number 2): https://www.reddit.com/r/chipdesign/comments/1unkvvz/reddit_designed_asic/

Credit to u/thegreatpotatogod for this terrible idea!

Both this post and the chip were created without any AI.

Hello everyone,

I’m a PI Engineer 1 at a major company in Vietnam with deep experience in RTL, STA, synthesis, and full-chip flow. I also have some hands-on experience using HSPICE to simulate and characterize CMOS analog blocks (amplifiers, LDOs, current references, etc.).

I’m very interested in switching to Analog IC Design (especially RF, mmWave, or biomedical applications) and am currently preparing Master’s applications at top research groups in Taiwan (NTU, NTHU, NCKU, NCTU, etc.). I would really appreciate any insights or advice from people who have experience in these programs.

Here are my main questions:

1. Do any of these labs accept and train new Master’s students who have no prior analog background (only digital design or CMOS simulation experience)?
2. If accepted, how long does it typically take for students to be fully trained and start contributing real work (e.g., designing analog blocks and participating in tape-out projects)?

Additionally, is it realistic after 2 years in a Master’s program to complete:

• Tape-out of 1 analog chip (single block or small IP)
• Publication of 1–2 papers in international conferences