hi i finished my first project in system verilog. i built a multicycle riscv32i cpu core this is my first actual project with system verilog or with hdl ever so i would like to get some notes code wise because i dont actually know a lot about naming conventions module declarations etc. code

renulev/sap-1: Malvino's SAP-1 implemented in Verilog

I used Icarus verilog for this project. GTKWave output looks clean.
I also used Makefile for automation.

I made forwardpropagation in CNN, but i dont know what is backporpagation work on fpga. I read many documents about this topic but they just do it on python language, but i want to do that on fpga by verilog language. Can someone give me some solutions or advice

This document closest my mind: https://link.springer.com/article/10.1007/s11554-021-01147-2#Tab2

Hi, Almost dead Computer Engineering redditors.
I have a Computer Systems Architecture Course and I want to implement a 3 state Kalman Filter in Vivado. I'll get Real time data from Gy-87 (MPU-6050), through Esp-32 into my pc. Now the problem is idk how to get it into Vivado without an FPGA. I'm a sopho in uni with this being our first technical CE course. Any help is appreciated.
And where do i learn system verilog properly?

i am starting my career in vlsi ...
can anyone suggest a clear cut roadmap for me any best resources , how to utilise them and make my work easier
i would love to connect and learn